[PATCH] D124839: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling (WIP)

Wed May 4 07:24:23 PDT 2022

RKSimon added inline comments.

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Comment at: llvm/test/CodeGen/ARM/ror.ll:24-31
+; CHECK-NEXT:    bic r2, r0, #15
+; CHECK-NEXT:    ror r0, r0, #4
+; CHECK-NEXT:    lsr r0, r0, #6
+; CHECK-NEXT:    orr r0, r0, r2, lsl #22
+; CHECK-NEXT:    bic r2, r1, #15
+; CHECK-NEXT:    ror r1, r1, #4
+; CHECK-NEXT:    lsr r1, r1, #6
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dmgreen wrote:
> Is this still an issue if the IR is canonically using fshr? https://godbolt.org/z/EMnGsq9nT
No, if we can assume the IR has come from the middle end then it will be 2 FSHLR funnel shift intrinsics and will fold correctly. If this codegen can appear in DAG then its a regression.

I'm happy to update the tests to use the fshl/fshr intrinsics?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124839/new/

https://reviews.llvm.org/D124839