[PATCH] D124839: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling (WIP)

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/test/CodeGen/ARM/ror.ll:24-31
+; CHECK-NEXT:    bic r2, r0, #15
+; CHECK-NEXT:    ror r0, r0, #4
+; CHECK-NEXT:    lsr r0, r0, #6
+; CHECK-NEXT:    orr r0, r0, r2, lsl #22
+; CHECK-NEXT:    bic r2, r1, #15
+; CHECK-NEXT:    ror r1, r1, #4
+; CHECK-NEXT:    lsr r1, r1, #6
----------------
RKSimon wrote:
> dmgreen wrote:
> > Is this still an issue if the IR is canonically using fshr? https://godbolt.org/z/EMnGsq9nT
> No, if we can assume the IR has come from the middle end then it will be 2 FSHLR funnel shift intrinsics and will fold correctly. If this codegen can appear in DAG then its a regression.
> 
> I'm happy to update the tests to use the fshl/fshr intrinsics?
Yeah, adding the new test for the canonical form sounds useful, to show it's not getting worse. Whether optimizing something like this would be useful or not, I'm not sure. It sounds unlikely to come up.
```
      t19: v2i32 = BUILD_VECTOR Constant:i32<28>, Constant:i32<28>
    t52: v2i32 = rotl t17, t19
    t29: v2i32 = BUILD_VECTOR Constant:i32<6>, Constant:i32<6>
  t30: v2i32 = srl t52, t29
      t22: v2i32 = BUILD_VECTOR Constant:i32<4>, Constant:i32<4>
    t23: v2i32 = srl t17, t22
    t26: v2i32 = BUILD_VECTOR Constant:i32<26>, Constant:i32<26>
  t51: v2i32 = shl t23, t26
t31: v2i32 = or t30, t51

```


Repository:
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  https://reviews.llvm.org/D124839/new/

https://reviews.llvm.org/D124839