[PATCH] D124839: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling (WIP)

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/test/CodeGen/ARM/ror.ll:24-31
+; CHECK-NEXT:    bic r2, r0, #15
+; CHECK-NEXT:    ror r0, r0, #4
+; CHECK-NEXT:    lsr r0, r0, #6
+; CHECK-NEXT:    orr r0, r0, r2, lsl #22
+; CHECK-NEXT:    bic r2, r1, #15
+; CHECK-NEXT:    ror r1, r1, #4
+; CHECK-NEXT:    lsr r1, r1, #6
----------------
Is this still an issue if the IR is canonically using fshr? https://godbolt.org/z/EMnGsq9nT


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124839/new/

https://reviews.llvm.org/D124839