[PATCH] D124839: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling (WIP)

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> AMDGPU - we're losing a v2i16 splat pattern

I'm not 100% sure but I think this might be fixed if we did a better job of optimizing this fragment of DAG:

  Legalized selection DAG:
  
            t33: v2i32 = scalar_to_vector t36
          t66: i64 = bitcast t33
        t67: i64 = srl t66, Constant:i32<16>
      t68: i16 = truncate t67
    t69: i32 = zero_extend t68

Currently gets "optimized" to:

  Optimized legalized selection DAG:
  
          t33: v2i32 = scalar_to_vector t36
        t66: i64 = bitcast t33
      t67: i64 = srl t66, Constant:i32<16>
    t73: i32 = truncate t67

But the whole thing could just be `t73: i32 = srl t36, Constant:i32<16>`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124839/new/

https://reviews.llvm.org/D124839