[PATCH] D124839: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

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Pulled out of D77804 <https://reviews.llvm.org/D77804> as its going to be easier to address the regressions individually.

This patch enables us to peek through the shifted value if we don't demand all the bits/elts.

Current regressions I'm still addressing (suggestions welcome)

AMDGPU - we're losing a v2i16 splat pattern
ARM - failure to fold funnel shifts by constants pre-legalization
RISCV - I'm not certain if the lost gorc2 fold is a problem - instcombine would have already destroyed that pattern - see https://github.com/llvm/llvm-project/issues/50553


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124839

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/ARM/ror.ll
  llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/rv32zbp-zbkb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
  llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
  llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
  llvm/test/CodeGen/X86/load-local-v3i129.ll
  llvm/test/CodeGen/X86/mul128.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

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