[PATCH] D120958: [TableGen] Add support for variable length instruction in decoder generator

Sheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 3 20:00:48 PDT 2022


0x59616e added a comment.

In D120958#3490184 <https://reviews.llvm.org/D120958#3490184>, @0x59616e wrote:

> In D120958#3487811 <https://reviews.llvm.org/D120958#3487811>, @foad wrote:
>
>> For the record, to get this to build with my downstream target, I had to add:
>>
>>   MyInsnType MyInsnType::operator&(const uint64_t &RHS);
>>   bool MyInsnType::operator!=(const int &RHS);
>
> Thanks for your information. I'll update the comment.

@myhsu  Should we define our own inst type that wraps APInt, or update the comment and maintain the status quo ?


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https://reviews.llvm.org/D120958



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