[PATCH] D120958: [TableGen] Add support for variable length instruction in decoder generator

[Todd Snider via Phabricator via llvm-commits]

snidertm added inline comments.


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Comment at: llvm/test/TableGen/VarLenDecoder.td:50
+// CHECK-NEXT: MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12
+// CHECK-NEXT: MCD::OPC_Decode, 244, 1, 0, // Opcode: FOO16
+// CHECK-NEXT: MCD::OPC_FilterValue, 9, 4, 0, 0, // Skip to: 21
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Is 244 the index into the instruction table where FOO16 is expected to reside?

This check on OPC_Decode seems extremely brittle. If there are any additions either in the upstream Target.td or in a downstream Target.td, won't this check and the one on line 52 will break?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120958/new/

https://reviews.llvm.org/D120958