[PATCH] D120958: [TableGen] Add support for variable length instruction in decoder generator

[Sheng via Phabricator via llvm-commits]

0x59616e added a comment.

In D120958#3487811 <https://reviews.llvm.org/D120958#3487811>, @foad wrote:

> For the record, to get this to build with my downstream target, I had to add:
>
>   MyInsnType MyInsnType::operator&(const uint64_t &RHS);
>   bool MyInsnType::operator!=(const int &RHS);

Thanks for your information. I'll update the comment.


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  https://reviews.llvm.org/D120958/new/

https://reviews.llvm.org/D120958