[PATCH] D124820: [RISCV][WIP] Update isLegalAddressingMode for RVV.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1021
 
+  // RVV instructions only support register addressing.
+  if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
----------------
reames wrote:
> Placement wise, this makes more sense at the top so that all of the scalar checks are grouped together. 
Top, or just above the 12-bit offset check?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124820/new/

https://reviews.llvm.org/D124820