[PATCH] D124820: [RISCV][WIP] Update isLegalAddressingMode for RVV.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/comment addressed.

I applied this locally and checked a couple of hand written vector loops I'm using to get myself started, and the results look entirely reasonable.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1021
 
+  // RVV instructions only support register addressing.
+  if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
----------------
Placement wise, this makes more sense at the top so that all of the scalar checks are grouped together. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D124820/new/

https://reviews.llvm.org/D124820