[PATCH] D124820: [RISCV][WIP] Update isLegalAddressingMode for RVV.

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1021
 
+  // RVV instructions only support register addressing.
+  if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
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craig.topper wrote:
> reames wrote:
> > Placement wise, this makes more sense at the top so that all of the scalar checks are grouped together. 
> Top, or just above the 12-bit offset check?
Ah, you're right.

Or alternately, top, and duplicate the BaseGV check.  

Either is fine.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124820/new/

https://reviews.llvm.org/D124820