[PATCH] D124820: [RISCV][WIP] Update isLegalAddressingMode for RVV.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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RVV instructions only support base register addressing.

Probably need more directed LSR tests and maybe CodeGenPrepare.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124820

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll


Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
@@ -596,7 +596,6 @@
 ;
 ; CHECK-ASM-LABEL: struct_gather:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    addi a0, a0, 32
 ; CHECK-ASM-NEXT:    addi a1, a1, 132
 ; CHECK-ASM-NEXT:    li a2, 1024
 ; CHECK-ASM-NEXT:    li a3, 16
@@ -606,13 +605,13 @@
 ; CHECK-ASM-NEXT:    vsetivli zero, 8, e32, m1, ta, mu
 ; CHECK-ASM-NEXT:    vlse32.v v8, (a4), a3
 ; CHECK-ASM-NEXT:    vlse32.v v9, (a1), a3
-; CHECK-ASM-NEXT:    addi a4, a0, -32
-; CHECK-ASM-NEXT:    vle32.v v10, (a4)
-; CHECK-ASM-NEXT:    vle32.v v11, (a0)
+; CHECK-ASM-NEXT:    vle32.v v10, (a0)
+; CHECK-ASM-NEXT:    addi a4, a0, 32
+; CHECK-ASM-NEXT:    vle32.v v11, (a4)
 ; CHECK-ASM-NEXT:    vadd.vv v8, v10, v8
 ; CHECK-ASM-NEXT:    vadd.vv v9, v11, v9
-; CHECK-ASM-NEXT:    vse32.v v8, (a4)
-; CHECK-ASM-NEXT:    vse32.v v9, (a0)
+; CHECK-ASM-NEXT:    vse32.v v8, (a0)
+; CHECK-ASM-NEXT:    vse32.v v9, (a4)
 ; CHECK-ASM-NEXT:    addi a2, a2, -16
 ; CHECK-ASM-NEXT:    addi a0, a0, 64
 ; CHECK-ASM-NEXT:    addi a1, a1, 256
@@ -838,17 +837,16 @@
 ;
 ; CHECK-ASM-LABEL: gather_of_pointers:
 ; CHECK-ASM:       # %bb.0:
-; CHECK-ASM-NEXT:    addi a0, a0, 16
 ; CHECK-ASM-NEXT:    li a2, 1024
 ; CHECK-ASM-NEXT:    li a3, 40
 ; CHECK-ASM-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; CHECK-ASM-NEXT:    addi a4, a1, 80
 ; CHECK-ASM-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; CHECK-ASM-NEXT:    vlse64.v v8, (a1), a3
+; CHECK-ASM-NEXT:    addi a4, a1, 80
 ; CHECK-ASM-NEXT:    vlse64.v v9, (a4), a3
-; CHECK-ASM-NEXT:    addi a4, a0, -16
-; CHECK-ASM-NEXT:    vse64.v v8, (a4)
-; CHECK-ASM-NEXT:    vse64.v v9, (a0)
+; CHECK-ASM-NEXT:    vse64.v v8, (a0)
+; CHECK-ASM-NEXT:    addi a4, a0, 16
+; CHECK-ASM-NEXT:    vse64.v v9, (a4)
 ; CHECK-ASM-NEXT:    addi a2, a2, -4
 ; CHECK-ASM-NEXT:    addi a0, a0, 32
 ; CHECK-ASM-NEXT:    addi a1, a1, 160
@@ -912,14 +910,13 @@
 ;
 ; CHECK-ASM-LABEL: scatter_of_pointers:
 ; CHECK-ASM:       # %bb.0:
-; CHECK-ASM-NEXT:    addi a1, a1, 16
 ; CHECK-ASM-NEXT:    li a2, 1024
 ; CHECK-ASM-NEXT:    li a3, 40
 ; CHECK-ASM-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; CHECK-ASM-NEXT:    addi a4, a1, -16
 ; CHECK-ASM-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-ASM-NEXT:    vle64.v v8, (a4)
-; CHECK-ASM-NEXT:    vle64.v v9, (a1)
+; CHECK-ASM-NEXT:    vle64.v v8, (a1)
+; CHECK-ASM-NEXT:    addi a4, a1, 16
+; CHECK-ASM-NEXT:    vle64.v v9, (a4)
 ; CHECK-ASM-NEXT:    addi a4, a0, 80
 ; CHECK-ASM-NEXT:    vsse64.v v8, (a0), a3
 ; CHECK-ASM-NEXT:    vsse64.v v9, (a4), a3
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1018,6 +1018,10 @@
   if (!isInt<12>(AM.BaseOffs))
     return false;
 
+  // RVV instructions only support register addressing.
+  if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
+    return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs;
+
   switch (AM.Scale) {
   case 0: // "r+i" or just "i", depending on HasBaseReg.
     break;


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