[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added a comment.

Nice change(s).
I’m not sure why the writelane registers are added as live-in to every block. Is the same happening for WWM registers and VGPRs used for SGPR spills?



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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1267-1269
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getLaneVGPRs())
+      MBB.addLiveIn(Reg.first);
----------------
Why do we need these registers as a live-in to every block? (do we also need them as live-out if they should be alive everywhere?)


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:506
+  SmallVector<Register, 2> SpillVGPRs;
+  using LaneVGPRsMap = MapVector<Register, Optional<int>>;
+  LaneVGPRsMap LaneVGPRs;
----------------
hsmhsm wrote:
> Why do we need `MapVector` here instead of DenseMap? Do we need to access the values in deterministic order?
I guess if it’s not deterministic, the spills and restores will be in an undefined order and we get different results when compiling multiple times


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  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192