[llvm] 9534811 - [RISCV] Teach generateInstSeqImpl to generate BSETI for single bit cases.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-04-21T12:08:34-07:00
New Revision: 9534811aa8dddec84520776ec027721f062362eb

URL: https://github.com/llvm/llvm-project/commit/9534811aa8dddec84520776ec027721f062362eb
DIFF: https://github.com/llvm/llvm-project/commit/9534811aa8dddec84520776ec027721f062362eb.diff

LOG: [RISCV] Teach generateInstSeqImpl to generate BSETI for single bit cases.

If the immediate has one bit set, but isn't a simm32 we can try
the BSETI instruction from Zbs.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    llvm/test/CodeGen/RISCV/imm.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index b651ee04a6145..e70acf07cf872 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -73,6 +73,12 @@ static void generateInstSeqImpl(int64_t Val,
 
   assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
 
+  // Use BSETI for a single bit.
+  if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val)) {
+    Res.push_back(RISCVMatInt::Inst(RISCV::BSETI, Log2_64(Val)));
+    return;
+  }
+
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
   // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
   // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits

diff  --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index 1a9f9b872bf0e..a5571c5a43a7e 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -354,8 +354,7 @@ define i64 @imm64_1() nounwind {
 ;
 ; RV64IZBS-LABEL: imm64_1:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    li a0, 1
-; RV64IZBS-NEXT:    slli a0, a0, 31
+; RV64IZBS-NEXT:    bseti a0, zero, 31
 ; RV64IZBS-NEXT:    ret
   ret i64 2147483648 ; 0x8000_0000
 }
@@ -420,8 +419,7 @@ define i64 @imm64_3() nounwind {
 ;
 ; RV64IZBS-LABEL: imm64_3:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    li a0, 1
-; RV64IZBS-NEXT:    slli a0, a0, 32
+; RV64IZBS-NEXT:    bseti a0, zero, 32
 ; RV64IZBS-NEXT:    ret
   ret i64 4294967296 ; 0x1_0000_0000
 }
@@ -453,8 +451,7 @@ define i64 @imm64_4() nounwind {
 ;
 ; RV64IZBS-LABEL: imm64_4:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    li a0, -1
-; RV64IZBS-NEXT:    slli a0, a0, 63
+; RV64IZBS-NEXT:    bseti a0, zero, 63
 ; RV64IZBS-NEXT:    ret
   ret i64 9223372036854775808 ; 0x8000_0000_0000_0000
 }
@@ -486,8 +483,7 @@ define i64 @imm64_5() nounwind {
 ;
 ; RV64IZBS-LABEL: imm64_5:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    li a0, -1
-; RV64IZBS-NEXT:    slli a0, a0, 63
+; RV64IZBS-NEXT:    bseti a0, zero, 63
 ; RV64IZBS-NEXT:    ret
   ret i64 -9223372036854775808 ; 0x8000_0000_0000_0000
 }