[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Mahesha S via Phabricator via llvm-commits]

hsmhsm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:505
   unsigned NumVGPRSpillLanes = 0;
-  SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
 
----------------
Are we still using the data structure `SGPRSpillVGPR`? If not, should not we delete it?


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:506
+  SmallVector<Register, 2> SpillVGPRs;
+  using LaneVGPRsMap = MapVector<Register, Optional<int>>;
+  LaneVGPRsMap LaneVGPRs;
----------------
Why do we need `MapVector` here instead of DenseMap? Do we need to access the values in deterministic order?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192