[PATCH] D123988: [LoongArch] Add basic floating-point instructions definition

Xi Ruoyao via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 20 23:48:42 PDT 2022


xry111 added inline comments.


================
Comment at: llvm/test/MC/LoongArch/Basic/Float/d-invalid.s:3
+
+# CHECK: :[[#@LINE+1]]:1: error: instruction requires the following: LA64 Basic Integer and Privilege Instruction Set
+movgr2fr.d $fa0, $a0
----------------
xen0n wrote:
> SixWeining wrote:
> > xen0n wrote:
> > > `movgr2fr.d` is not part of the D extension?
> > Yes, movgr2fr.d is part of the D extension. But this test checks it is not available on LA32 as [[ https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_movgr2fr_wd_movgr2frh_w | the document ]] says:
> > 
> > ```
> > MOVGR2FR.D writes the 64-bit value of general register rj into floating-point register fd.
> > ```
> > 
> > On LA32, general register is 32-bit but not 64-bit. So `MOVGR2FR.D` is not available.
> Hmm, for me the message comes as a bit of surprise, because it seems I'm getting asked for integer ISA on a FP insn; I don't know what others (i.e. RISC-V) are doing in this case though (memory is failing me and I cannot devote much time to LLVM before mid-May due to `$DAY_JOB`).
RV uses `let Predicates = [HasStdExtD, IsRV64]` for FMV_D_X, so I guess it will emit a general "unrecognized instruction" diagnostic.


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  https://reviews.llvm.org/D123988/new/

https://reviews.llvm.org/D123988



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