[PATCH] D123264: [RISCV] Pre-RA expand pseudos pass

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

> - Although I haven't run into that problem, I think it's still possible for an ADDI to become out of range of the AUIPC it refers to, if other passes move them too far apart. For branches we have the branch relaxation pass to solve essentially the same problem. Are we going to need a similar pass for AUIPC/ADDI? Or can we prevent this from happening?

This doesn't make sense to me? The immediate for the ADDI is unused in the .o file, and in the linked file it's just the low 12 bits of the 32-bit offset of the symbol from the AUIPC. Where you put the ADDI never matters, so long as it's in the same input section as the AUIPC its relocation refers to.



================
Comment at: llvm/lib/CodeGen/MachineInstr.cpp:634
+  // If pre- or post-instruction symbols do not match then the two instructions
+  // are not identical.
+  if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
----------------
This is overly strict in the specific case being addressed by this patch:
```
1: auipc a0, %pcrel_hi(foo)
   lw a1, %pcrel_lo(1b)(a0)
   addi a1, a1, 1
2: auipc a0, %pcrel_hi(foo)
   sw a1, %pcrel_lo(2b)(a0)
```
can legally be optimised to
```
1: auipc a0, %pcrel_hi(foo)
   lw a1, %pcrel_lo(1b)(a0)
   addi a1, a1, 1
   sw a1, %pcrel_lo(1b)(a0)
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123264/new/

https://reviews.llvm.org/D123264