[llvm] a0f9e4e - llvm-reduce: Fix handling of generic virtual registers

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-04-14T20:21:22-04:00
New Revision: a0f9e4ed2a472f0a41a4d292a9c5fc939ae064ad

URL: https://github.com/llvm/llvm-project/commit/a0f9e4ed2a472f0a41a4d292a9c5fc939ae064ad
DIFF: https://github.com/llvm/llvm-project/commit/a0f9e4ed2a472f0a41a4d292a9c5fc939ae064ad.diff

LOG: llvm-reduce: Fix handling of generic virtual registers

Try to preserve register banks, types and names. Fixes the lowest
hanging fruit in issue 54894.

Added: 
    llvm/test/tools/llvm-reduce/mir/generic-vreg.mir

Modified: 
    llvm/tools/llvm-reduce/ReducerWorkItem.cpp
    llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir b/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
new file mode 100644
index 0000000000000..0e3ffc8d3b8db
--- /dev/null
+++ b/llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
@@ -0,0 +1,42 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# Verify that reduction works with generic virtual registers, and the
+# properties like register banks, types and names.
+
+
+# CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
+# CHECK-INTERESTINGNESS: G_BITCAST
+# CHECK-INTERESTINGNESS: G_ADD
+# CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
+# CHECK-INTERESTINGNESS: G_STORE
+
+# RESULT: %v0:vgpr(s32) = COPY $vgpr0, implicit-def %9(p1), implicit-def %10(s64), implicit-def %11(s64)
+# RESULT-NEXT: %arst:_(<2 x s32>) = G_IMPLICIT_DEF
+# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %arst(<2 x s32>)
+# RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
+# RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
+# RESULT-NEXT: G_STORE %v0(s32), %ptr(p1) :: (store (s32), addrspace 1)
+# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %v0(s32), implicit %11(s64)
+
+---
+name:            f
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
+    %v0:vgpr(s32) = COPY $vgpr0
+    %v1:vgpr(<2 x s16>) = COPY $vgpr1
+    %unused_load_ptr:sgpr(p1) = G_IMPLICIT_DEF
+    %unused_load:_(s64) = G_LOAD %unused_load_ptr :: (load (s64), addrspace 1)
+    G_STORE %unused_load, %unused_load_ptr :: (store (s64), addrspace 1)
+    %2:vreg_64(s64) = COPY $vgpr2_vgpr3
+    %arst:_(<2 x s32>) = G_IMPLICIT_DEF
+    %aoeu:_(s64) = G_BITCAST %arst
+    S_NOP 0
+    %add:_(s64) = G_ADD %aoeu, %aoeu
+    %ptr:_(p1) = G_IMPLICIT_DEF
+    G_STORE %v0, %ptr :: (store 4, addrspace 1)
+    S_ENDPGM 0, implicit %add, implicit %v1, implicit %2
+...

diff  --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 96a0a7d5c72c5..456c90d4f37a8 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -40,8 +40,14 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF) {
         Register SrcReg = DMO.getReg();
         if (Register::isPhysicalRegister(SrcReg))
           continue;
-        auto SrcRC = SrcMRI->getRegClass(SrcReg);
-        auto DstReg = DstMRI->createVirtualRegister(SrcRC);
+        Register DstReg = DstMRI->createIncompleteVirtualRegister(
+            SrcMRI->getVRegName(SrcReg));
+        DstMRI->setRegClassOrRegBank(DstReg,
+                                     SrcMRI->getRegClassOrRegBank(SrcReg));
+
+        LLT RegTy = SrcMRI->getType(SrcReg);
+        if (RegTy.isValid())
+          DstMRI->setType(DstReg, RegTy);
         Src2DstReg[SrcReg] = DstReg;
       }
     }

diff  --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
index e64d6f3c5ee1b..29191b597a5da 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -23,7 +23,7 @@ using namespace llvm;
 
 static Register getPrevDefOfRCInMBB(MachineBasicBlock &MBB,
                                     MachineBasicBlock::reverse_iterator &RI,
-                                    const TargetRegisterClass *RC,
+                                    const RegClassOrRegBank &RC,
                                     SetVector<MachineInstr *> &ExcludeMIs) {
   auto MRI = &MBB.getParent()->getRegInfo();
   for (MachineBasicBlock::reverse_instr_iterator E = MBB.instr_rend(); RI != E;
@@ -37,7 +37,8 @@ static Register getPrevDefOfRCInMBB(MachineBasicBlock &MBB,
       if (Register::isPhysicalRegister(Reg))
         continue;
 
-      if (MRI->getRegClass(Reg) == RC && !ExcludeMIs.count(MO.getParent()))
+      if (MRI->getRegClassOrRegBank(Reg) == RC &&
+          !ExcludeMIs.count(MO.getParent()))
         return Reg;
     }
   }
@@ -79,7 +80,7 @@ static void extractInstrFromModule(Oracle &O, MachineFunction &MF) {
       auto UI = MRI->use_begin(Reg);
       auto UE = MRI->use_end();
 
-      auto RegRC = MRI->getRegClass(Reg);
+      const auto &RegRC = MRI->getRegClassOrRegBank(Reg);
       Register NewReg = 0;
       // If this is not a physical register and there are some uses.
       if (UI != UE) {
@@ -101,7 +102,7 @@ static void extractInstrFromModule(Oracle &O, MachineFunction &MF) {
       // If no dominating definition was found then add an implicit one to the
       // first instruction in the entry block.
       if (!NewReg && TopMI) {
-        NewReg = MRI->createVirtualRegister(RegRC);
+        NewReg = MRI->cloneVirtualRegister(Reg);
         TopMI->addOperand(MachineOperand::CreateReg(
             NewReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
       }