[llvm] b4ace5d - llvm-reduce: Fix asserting on undef virtual registers

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-04-14T20:21:22-04:00
New Revision: b4ace5da45672bbfa36c9adc74f5399d1ccd8a65

URL: https://github.com/llvm/llvm-project/commit/b4ace5da45672bbfa36c9adc74f5399d1ccd8a65
DIFF: https://github.com/llvm/llvm-project/commit/b4ace5da45672bbfa36c9adc74f5399d1ccd8a65.diff

LOG: llvm-reduce: Fix asserting on undef virtual registers

This was only populating the virtual register map for def operands
that appeared in the function, but that may not exist if there are
only undef uses.

Added: 
    llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir

Modified: 
    llvm/tools/llvm-reduce/ReducerWorkItem.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir b/llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
new file mode 100644
index 0000000000000..621281153379b
--- /dev/null
+++ b/llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir
@@ -0,0 +1,20 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: S_NOP 0
+
+# RESULT: S_ENDPGM 0, implicit undef %0:vgpr_32
+
+# Previously the the function clone would assert due to not preserving
+# virtual registers which had no defs.
+
+---
+name: undef_vreg_operand
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    S_NOP 0
+    S_ENDPGM 0, implicit undef %0:vgpr_32
+
+...

diff  --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 456c90d4f37a8..66fe653af518f 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -35,11 +35,15 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF) {
     for (auto &SrcMI : SrcMBB) {
       for (unsigned I = 0, E = SrcMI.getNumOperands(); I < E; ++I) {
         auto &DMO = SrcMI.getOperand(I);
-        if (!DMO.isReg() || !DMO.isDef())
+        if (!DMO.isReg())
           continue;
         Register SrcReg = DMO.getReg();
         if (Register::isPhysicalRegister(SrcReg))
           continue;
+
+        if (Src2DstReg.find(SrcReg) != Src2DstReg.end())
+          continue;
+
         Register DstReg = DstMRI->createIncompleteVirtualRegister(
             SrcMRI->getVRegName(SrcReg));
         DstMRI->setRegClassOrRegBank(DstReg,