[PATCH] D122829: [AArch64] Optimize SDIV with pow2 constant divisor

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added a comment.

In D122829#3420547 <https://reviews.llvm.org/D122829#3420547>, @dmgreen wrote:

> In D122829#3420108 <https://reviews.llvm.org/D122829#3420108>, @efriedma wrote:
>
>> If I'm following correctly, this is essentially reverting D4438 <https://reviews.llvm.org/D4438> .  It was implemented that way at the time to avoid the complex `add w8, w0, w8, lsr #26` operation. Reverting that isn't obviously an improvement; I don't think ARM microarchitecture has significantly changed in this respect since the last time it was measured.
>
> Yeah I was wondering what made this better. It's smaller at least, which is good. It should probably be used at minsize if it isn't already. But this kind of shows that it's not necessarily better, if the add and cmp can be executed in parallel, and the add+shift is 2 cycles: https://godbolt.org/z/3zvhxPbsP

I think AArch64's current BuildSDIVPow2 has two AArch64ISD which means less optinuity to combine.

Add with shift can be implemented by 3 ways:

1. Split to two micro op, one add one shift, it is always slower than independent add+cmp.
2. One pipeline stage to do the shift, generally it can get better IPC than independent add+cmp but the worst case will be slower than independent add+cmp.
3. Direct three input combinational logic circuit, it is always better than independent add+cmp.

I know some of Arm processor use case 2 but can someone tell me which way the mainstream AArch64 processor is.

And if we confirmed add with shift is really slower, how about the gcc's implementation for mod (2^N) ?

  negs    w1, w0
  negs    w1, w0
  and     w0, w0, 15
  and     w1, w1, 15
  csneg   w0, w0, w1, mi
  ret

current clang

  add     w8, w0, #15
  cmp     w0, #0
  csel    w8, w8, w0, lt
  and     w8, w8, #0xfffffff0
  sub     w0, w0, w8
  ret


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122829/new/

https://reviews.llvm.org/D122829