[PATCH] D122829: [AArch64] Optimize SDIV with pow2 constant divisor

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

In D122829#3420108 <https://reviews.llvm.org/D122829#3420108>, @efriedma wrote:

> If I'm following correctly, this is essentially reverting D4438 <https://reviews.llvm.org/D4438> .  It was implemented that way at the time to avoid the complex `add w8, w0, w8, lsr #26` operation. Reverting that isn't obviously an improvement; I don't think ARM microarchitecture has significantly changed in this respect since the last time it was measured.

Yeah I was wondering what made this better. It's smaller at least, which is good. It should probably be used at minsize if it isn't already. But this kind of shows that it's not necessarily better, if the add and cmp can be executed in parallel, and the add+shift is 2 cycles: https://godbolt.org/z/3zvhxPbsP


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