[PATCH] D122458: [RISCV][WIP] Enable TargetLowering::hasBitTest for masks that fit in ANDI.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Seems fine to me. If I'm seeing it correctly, we wouldn't expect any x86 or Hexagon changes because they don't check for a bit range, just any scalar type.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122458/new/

https://reviews.llvm.org/D122458