[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/i32-icmp.ll:179
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
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We need a more test case of -2050, which is the lower bound of simm12_sub1_exc0 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051