[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1222
+          (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_sub1_exc0:$imm)), 1)>;
+def : Pat<(setugt GPR:$rs1, simm12_sub1_exc0:$imm),
+          (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_sub1_exc0:$imm)), 1)>;
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For this setugt, it would be better to make a comment, the coresspondant positve value range of [-2049, -1], which is different on rv32 and rv64.


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Comment at: llvm/test/CodeGen/RISCV/i32-icmp.ll:228
+; RV32I-NEXT:    ret
+  %1 = icmp ult i32 %a, -2048
+  %2 = zext i1 %1 to i32
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Though the code is correct, it would be better to use positive number, which is more clear.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051