[PATCH] D121376: [RISCV][RVV] Introduce roundmode operand to PseudoVAADD instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/roundmode-insert.mir:26
+    dead $x0 = PseudoVSETVLI %2:gprnox0, 69, implicit-def $vl, implicit-def $vtype
+    %3:vr = PseudoVAADD_VV_MF8 %0:vr, %1:vr, 2, $noreg, 3, implicit $vxrm, implicit $vl, implicit $vtype
+    $v8 = COPY %3:vr
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arcbbb wrote:
> craig.topper wrote:
> > Does it really have an implicit $vxrm use before the RISCVVXRMRegister pass? @efriedma should we only have the vxrm use for the dynamic case?
> My observation is that `NoImplicit` is false by default in `CreateMachineInstr`, so implicit $vxrm is there since BuildMI.
Right SelectionDAG will do it from the tablegen definition. For scalar FP I didn't set uses FRM in the td file and then I do a PostProcesseISel to add it for DYN instructions.

Not sure if it makes sense to do something similar here. The VXRMRegister pass would need to add the implicit def once it added the CSR write.


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  https://reviews.llvm.org/D121376/new/

https://reviews.llvm.org/D121376