[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:354
 
+// A 12-bit signed immediate sub one where the imm range will be -2049~2046.
+def simm12_sub1 : ImmLeaf<XLenVT,
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craig.topper wrote:
> Can we use [-2049, 2046] to describe the range like the comments on AddiPair? That's a more common way to represent a range. The ~ character in there is weird. Please update the comment on simm12_plus1 as well.
done


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Comment at: llvm/test/CodeGen/RISCV/arith-with-overflow.ll:32
+; RV32I-NEXT:    slt a0, a3, a0
+; RV32I-NEXT:    slti a1, a1, 1
+; RV32I-NEXT:    xori a1, a1, 1
----------------
craig.topper wrote:
> This looks like a regression
sgtz a3 a1 ------> slt  a3, X0, a1
slt a3, X0, a1---->slti a1, a1, 1 + xori a1, a1, 1
I think the result of the above assembly conversion is correct， which can reduce the registers use.


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  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051