[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:355
+// A 12-bit signed immediate sub one where the imm range will be [-2049, 2046].
+def simm12_sub1 : ImmLeaf<XLenVT,
+  [{return (isInt<12>(Imm) && Imm != 2047) || Imm == -2049;}]>;
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The zero value should be excluded, which is not needed to do `li`, and case just 
 be used with the register `X0`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051