[PATCH] D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination

[Alexander via Phabricator via llvm-commits]

alex-t added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2237
+        bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum));
+        bool LiveSCC = RS->isRegUsed(AMDGPU::SCC);
+        const TargetRegisterClass *RC = IsSALU && !LiveSCC
----------------
rampitec wrote:
> Is not isRegUsed for the whole function and will always return true on practice?
This function is used to determine if SCC is live in all other places around the code.
Another option is to scan upwards until the block start is reached.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2254
+          if (IsSALU && !LiveSCC)
+            Shift.getInstr()->getOperand(3).setIsDead(
+                true); // Mark SCC as dead.
----------------
rampitec wrote:
> Weird formatting.
This is clang-format. Otherwise lint complains


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121524/new/

https://reviews.llvm.org/D121524