[PATCH] D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

Need a testcase with alive scc.



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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2237
+        bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum));
+        bool LiveSCC = RS->isRegUsed(AMDGPU::SCC);
+        const TargetRegisterClass *RC = IsSALU && !LiveSCC
----------------
Is not isRegUsed for the whole function and will always return true on practice?


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2254
+          if (IsSALU && !LiveSCC)
+            Shift.getInstr()->getOperand(3).setIsDead(
+                true); // Mark SCC as dead.
----------------
Weird formatting.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2240
+                                                   : &AMDGPU::VGPR_32RegClass;
         bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32;
         Register ResultReg =
----------------
alex-t wrote:
> rampitec wrote:
> > Can probably be another mov?
> Never :)
Why cannot it be v_mov_b32_e64?


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Comment at: llvm/test/CodeGen/AMDGPU/frame-index.mir:1
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+
----------------
rampitec wrote:
> No need to pass -mattr=-promote-alloca -amdgpu-sroa=0.
Not done.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D121524/new/

https://reviews.llvm.org/D121524