[PATCH] D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask

[Haocong Lu via Phabricator via llvm-commits]

Luhaocong updated this revision to Diff 415344.
Luhaocong edited the summary of this revision.
Luhaocong added a comment.

1. Only do this selection for `and i64 %x, imm` when the `imm` exceeds simm32 (cannot be generated by LUI)
2. Add some test cases


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121598/new/

https://reviews.llvm.org/D121598

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/and.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D121598.415344.patch
Type: text/x-patch
Size: 10459 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220315/a7b05c13/attachment.bin>