[PATCH] D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/and.ll:121
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -1536
+; RV64I-NEXT:    and a0, a0, a1
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I just submitted D121650 to fix this case so it will sign extend -1536 to i64 instead of zero extending.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121598/new/

https://reviews.llvm.org/D121598