[PATCH] D121598: [RISCV] Select SRLI+SLLI for AND with leading ones mask

[Haocong Lu via Phabricator via llvm-commits]

Luhaocong marked an inline comment as done.
Luhaocong added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/copysign-casts.ll:32
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a3, 524288
-; RV32I-NEXT:    and a2, a2, a3
+; RV32I-NEXT:    srli a2, a2, 31
+; RV32I-NEXT:    slli a2, a2, 31
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craig.topper wrote:
> Is this worse if the AND is in a loop? The LUI could be hoisted out of the out loop, but the shifts can't.
if a leading ones mask can be generated by LUI, it's really unnecessary to do this. I have excluded this case.


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https://reviews.llvm.org/D121598