[PATCH] D120686: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

Chenbing.Zheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 1 18:00:15 PST 2022

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Chenbing.Zheng added a comment.
Herald added a project: All.

Looks great, what about other reviewer's opinions?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D120686/new/

https://reviews.llvm.org/D120686

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