[PATCH] D120686: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa1f8349d770f: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D120686?vs=412096&id=412471#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120686/new/

https://reviews.llvm.org/D120686

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

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