[PATCH] D120686: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 412096.
craig.topper added a comment.

Fixup some comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120686/new/

https://reviews.llvm.org/D120686

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

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