[PATCH] D120686: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7309
+// ROTR ((GREV x, 56), 32) -> (GREVI x, 24) for RV64
+// ROTL ((GREV x, 56), 32) -> (GREVI x, 24) for RV64
+// RORW ((GREVW x, 24), 16) -> (GREVIW x, 8) for RV64
----------------
Chenbing.Zheng wrote:
> Should tests be added for this case?
I added two new tests to rv64zbp.ll `bswap_rotr_i64` and `bswap_rotl_i64`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120686/new/

https://reviews.llvm.org/D120686