[PATCH] D120686: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7309
+// ROTR ((GREV x, 56), 32) -> (GREVI x, 24) for RV64
+// ROTL ((GREV x, 56), 32) -> (GREVI x, 24) for RV64
+// RORW ((GREVW x, 24), 16) -> (GREVIW x, 8) for RV64
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Should tests be added for this case?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120686/new/

https://reviews.llvm.org/D120686