[PATCH] D120226: [RISCV] Support mask policy for RVV IR intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:510
+  // are mask undisturbed.
+  bool MaskAgnostic = IsValidMaskPolicy ? true : false;
   // If the instruction has policy argument, use the argument.
----------------
We don't need a ternary operator here. IsValidMaskPolicy is a bool. You can do `bool MaskAgnostic = IsValidMaskPolicy`


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1155
   let HasMergeOp = 1;
+  let IsValidMaskPolicy = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
----------------
VPseudoBinaryMask appears to only be used by VPseudoTernary which is used by reductions. But reduction shouldn't have IsValidMaskPolicy?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120226/new/

https://reviews.llvm.org/D120226