[PATCH] D120001: [JITLink] Add R_RISCV_SUB6 relocation

[luxufan via Phabricator via llvm-commits]

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Add R_RISCV_SUB6 relocation


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120001

Files:
  llvm/include/llvm/ExecutionEngine/JITLink/riscv.h
  llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
  llvm/test/ExecutionEngine/JITLink/RISCV/riscv_reloc_add.s


Index: llvm/test/ExecutionEngine/JITLink/RISCV/riscv_reloc_add.s
===================================================================
--- llvm/test/ExecutionEngine/JITLink/RISCV/riscv_reloc_add.s
+++ llvm/test/ExecutionEngine/JITLink/RISCV/riscv_reloc_add.s
@@ -8,6 +8,7 @@
 # jitlink-check: *{4}(named_data+8) = 0x8
 # jitlink-check: *{2}(named_data+12) = 0x8
 # jitlink-check: *{1}(named_data+14) = 0x8
+# jitlink-check: *{1}(named_data+15) = 0x8
 
 .global main
 main:
@@ -20,8 +21,10 @@
 .section ".rodata","", at progbits
 .type named_data, at object
 named_data:
+.reloc named_data+15, R_RISCV_SUB6, .L0
 .dword .L1 - .L0
 .word .L1 - .L0
 .half .L1 - .L0
 .byte .L1 - .L0
-.size named_data, 15
+.byte 0x8
+.size named_data, 16
Index: llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
===================================================================
--- llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
+++ llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
@@ -358,6 +358,13 @@
       *FixupPtr = static_cast<uint8_t>(Value);
       break;
     }
+    case R_RISCV_SUB6: {
+      int64_t Value =
+          *(reinterpret_cast<const uint8_t *>(FixupAddress.getValue())) -
+          E.getTarget().getAddress().getValue() - E.getAddend();
+      *FixupPtr = (*FixupPtr & 0xc0) | static_cast<uint8_t>(Value);
+      break;
+    }
     case R_RISCV_SET6: {
       int64_t Value = (E.getTarget().getAddress() + E.getAddend()).getValue();
       uint32_t RawData = *(little32_t *)FixupPtr;
@@ -441,6 +448,8 @@
       return EdgeKind_riscv::R_RISCV_SUB16;
     case ELF::R_RISCV_SUB8:
       return EdgeKind_riscv::R_RISCV_SUB8;
+    case ELF::R_RISCV_SUB6:
+      return EdgeKind_riscv::R_RISCV_SUB6;
     case ELF::R_RISCV_SET6:
       return EdgeKind_riscv::R_RISCV_SET6;
     case ELF::R_RISCV_SET8:
Index: llvm/include/llvm/ExecutionEngine/JITLink/riscv.h
===================================================================
--- llvm/include/llvm/ExecutionEngine/JITLink/riscv.h
+++ llvm/include/llvm/ExecutionEngine/JITLink/riscv.h
@@ -145,6 +145,12 @@
   ///   Fixup <- (Target - *{1}Fixup - Addend)
   R_RISCV_SUB8,
 
+  /// 6 bits label subtraction
+  ///
+  /// Fixup expression
+  ///   Fixup <- (Target - *{1}Fixup - Addend)
+  R_RISCV_SUB6,
+
   /// Local label assignment
   ///
   /// Fixup expression:


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