[PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/X86/abs.ll:28
 ; X64:       # %bb.0:
-; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    movl %edi, %ecx
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    movl %eax, %ecx
----------------
jrtc27 wrote:
> Looks like we picked up an instruction here?
Yeah. The ADD we had before could be converted to LEA. But we can't do that for sub. i16 and above use cmov, but we have no i8 cmov.

FWIW, the new code matches gcc.

I think it's less likely to be an issue when we don't have a register allocation constraint from the top and bottom of the sequence.

If we're really concerned I an try custom selecting this back the old way for i8?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119171/new/

https://reviews.llvm.org/D119171