[PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll:1
-; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s
-; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s --check-prefix=THUMB
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craig.topper wrote:
> This test is likely no longer testing what it was before and I don't know how to fix it.
Presumably should be a MIR test that runs just the machine scheduler on a previously-broken instruction sequence?..


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Comment at: llvm/test/CodeGen/X86/abs.ll:28
 ; X64:       # %bb.0:
-; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    movl %edi, %ecx
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    movl %eax, %ecx
----------------
Looks like we picked up an instruction here?


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Comment at: llvm/test/CodeGen/X86/iabs.ll:24
 ; X64:       # %bb.0:
-; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    movl %edi, %ecx
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    movl %eax, %ecx
----------------
... and here


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Comment at: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected:1
 ; Example input for update_llc_test_checks (taken from CodeGen/X86/iabs.ll)
 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 --check-prefix=X86-NO-CMOV
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Heh, maybe basic.ll should be even more basic...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119171/new/

https://reviews.llvm.org/D119171