[PATCH] D119346: [AArch64][SVE] Perform fixed-width predicate OR reduction on SVE predicate vectors.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14379
+    for (auto *Use : N->uses())
+      DCI.AddToWorklist(Use);
+  }
----------------
This feels weird; we're adding nodes to the worklist without having actually done any transforms.  Maybe this should be somewhere else?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll:372
 ; CHECK-NEXT:    fcmne p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    not p1.b, p2/z, p1.b
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
----------------
This is a nice improvement.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll:19
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
 ; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
----------------
We should probably prefer to do this unpacking in predicate registers.  But not necessary for this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119346/new/

https://reviews.llvm.org/D119346