[PATCH] D119346: [AArch64][SVE] Perform fixed-width predicate OR reduction on SVE predicate vectors.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: efriedma, paulwalker-arm, cameron.mcinally, bsmith, peterwaller-arm.
Herald added subscribers: ctetreau, psnobl, hiraditya, kristof.beyls, tschuett.
sdesmalen requested review of this revision.
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By default fixed-width i1 vectors are promoted, but when SVE is available,
some expression trees can be rewritten to use <vscale x M x i1> types,
such that all operations are performed on predicate registers, thus
avoiding unnecessary sign-extends and truncates. It does this by bubbling
up the 'sign-extend + extract' operations all the way up to nodes that
can be performed on SVE predicate registers.

The example chosen in this patch is to optimise an OR reduction
of a <N x i1> type, which can be implemented directly with a PTEST
instruction.

This patch is a rework of D117574 <https://reviews.llvm.org/D117574>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119346

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll

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