[PATCH] D117574: [AArch64][SVE] POC: Use predicate registers for <N x i1> expression trees.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

In D117574#3252523 <https://reviews.llvm.org/D117574#3252523>, @efriedma wrote:

> The other possible approach I can think of is to reconsider the way legalization works for i1 vectors.  This transform is basically reversing work done by type legalization: the legalizer promotes i1 vectors because they aren't legal.  We could, instead, use some sort of custom legalization for i1 vectors: instead of promoting the element type, convert them directly to scalable vectors.  Probably more work to implement initially.  But it might be easier to reason about the profitability if we avoid generating sign-extensions that shouldn't exist in the first place.
>
> Which approach is better depends on how complex propagatePredicateTy gets, I guess.  If we just have 100 lines of code to reverse sign-extensions, fine; if we end up with 1000 lines, probably we should reconsider the approach.

My understanding is that decisions have been made for NEON on how to represent fixed-width vectors of i1's (i.e. through promotion) and we're kind of bound to those choices going forward. This avoids mixing the two representations (or better: their definition of whether they are illegal/legal types) based on the amount of elements in the vector or on where the vectors are used. It seems doable to undo the type legalisation for certain cases, such as `vecreduce_or`. From what I've seen so far, I expect we'll need to support only a handful of cases to bubble up the sign-extend + extract_subvector.

I've simplified the approach and put up a new patch here: D119346 <https://reviews.llvm.org/D119346>


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