[PATCH] D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection

[Alexander via Phabricator via llvm-commits]

alex-t updated this revision to Diff 407210.
alex-t added a comment.

Odd comments and copy-paste typo corrected


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119302/new/

https://reviews.llvm.org/D119302

Files:
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
  llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
  llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll

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