[PATCH] D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection

Wed Feb 9 04:32:30 PST 2022

foad added a comment.

Looks OK but I don't understand the V_MOV vs S_MOV thing.

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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:1997
   (i16 (DivergentSextInreg<i8> i16:$src)),
   (V_BFE_I32_e64 $src, (i32 0), (i32 8)) // 0 | 8 << 16
 >;
----------------
These comments don't make any sense for V_BFE so I removed them and you'll have to rebase (sorry).

================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2252
+  (i32 (DivergentUnaryFrag<zext> i16:$src)),
+  (V_AND_B32_e64 (S_MOV_B32 (i32 0xffff)), $src)
+>;
----------------
Why S_MOV here...

================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2258
+  (REG_SEQUENCE VReg_64,
+    (V_AND_B32_e64 (V_MOV_B32_e32 (i32 0xffff)), $src), sub0,
+    (S_MOV_B32 (i32 0)), sub1)
----------------
... but V_MOV here?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119302/new/

https://reviews.llvm.org/D119302