[PATCH] D117574: [AArch64][SVE] POC: Use predicate registers for <N x i1> expression trees.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

For NEON, we're obviously forced to promote, sure.  And that means even if we have SVE, we're forced to promote across call boundaries.  That doesn't necessarily constrain what we do within a function; there's space to prefer SVE operations more aggressively.  But it makes things more complicated, sure.  In particular, we probably don't want to try to deal with all the side-effects if we try to mark the types "legal".

I think there are still potential alternatives to consider, though.  Maybe instead of actually using the type legalization machinery, we could DAGCombine operations involving fixed-width predicates before type legalization.  Or we can use custom lowering to generate some sequence that eventually produces a value of the right type, but is easier to analyze.  There's some space to explore here for representations of fixed-width SETCC that aren't just SETCC with a promoted result type.


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https://reviews.llvm.org/D117574