[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:720
+    defvar wti_m1 = !cast<VTypeInfo>("VI"#wti.SEW#"M1");
+    def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+                                 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
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frasercrmck wrote:
> To avoid introducing too many patterns to our table, which is already really big, after rebasing it'd help if you could try following D118810 and only introduce `V0` patterns, leaving the post-process step to optimize the unmasked cases.
The reductions are different than the instructions already handled in the post process. There is no merge operand for reductions so we can't drop operand 0.

This patch only adds widening reductions. That regular reductions are already present with masked and unmasked patterns. Given the change needed to the post-process, I think all the reductions should be done together as a separate patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117643/new/

https://reviews.llvm.org/D117643