[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:720
+    defvar wti_m1 = !cast<VTypeInfo>("VI"#wti.SEW#"M1");
+    def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+                                 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
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To avoid introducing too many patterns to our table, which is already really big, after rebasing it'd help if you could try following D118810 and only introduce `V0` patterns, leaving the post-process step to optimize the unmasked cases.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117643/new/

https://reviews.llvm.org/D117643