[PATCH] D117643: [RISCV] Add patterns for vector widening integer reduction instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Why are the tests only i32->i64?



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Comment at: llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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Can you update the rv32 test as well? These files should be kept in sync


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117643/new/

https://reviews.llvm.org/D117643